New Method of Building Switching Elements for Data Centers

The ever-growing increase in global internet traffic imposes significant challenges on data center (DC) operators and equipment manufacturers. An almost exponential growth is found for both intra- and inter-DC traffic originating from the continuous growth of cloud-based applications, social media, and big data analytics. Modern DCs utilize hundreds of thousands of servers in several hierarchy layers which require an efficient interconnection network which is both low-cost and energy-efficient. In addition, the switching platforms must support the high bandwidth required for large scale non-blocking topologies. These severe requirements are difficult to fulfil using conventional electronic packet switching and copper-based interconnection technologies with the main limitations arising from high power consumptions, limited reach, and increasing latency. The introduction of photonic technologies to the DC in the last years resulted in significant performance enhancement. However, the traffic increase requirements outpace the technological capabilities and new approaches were needed. Precisely addressing these challenges, the now successfully completed EU project “Large Scale Silicon Photonics Matrix for Low Power and Low-Cost Data Centers” (L3MATRIX) devised solutions for cost reduction, efficiency, and performance.

The research and innovation project L3MATRIX, “Large Scale Silicon Photonics Matrix for Low Power and Low-Cost Data Centers”, as co-funded by the Horizon 2020 Framework Programme of the European Union – ‘ICT-27-2015 – Photonics KET’, successfully completed  its activities. (Source: L3MATRIX.eu)

The L3MATRIX project provided novel technological innovations in the fields of silicon photonics (SiPh) and 3D device integration. The potential for network scaling to the Pb/s range is demonstrated by co-packaging the optical interconnects with the switching ASIC, thereby increasing the chip radix. The latter is the main limit to bandwidth scaling. The optical interconnect is implemented as a large, two-dimensional SiP matrix that provides both the required data density based on the parallel layout of the device, and long reach as it is a single mode optical solution. Packet parsing and switching is assigned to the ASIC. This solution is both low-cost and low-power due to the vertical integration of the optical matrix and CMOS logic chip. The on-chip assembly of the optical interconnect transceiver is a natural evolutionary step in the optical interconnect industry.

The outcome of this long reach photonic-digital integration ‘co-package’ is the creation of radically new system and network architectures that enable scaling of the network to Pb/s scale using a fraction of the devices that would be needed otherwise. The result is a 10x reduction of the power consumption since the number of switching devices is lower compared to the conventional technology. Latency is greatly reduced into the 10 – 20 ns range as the number of hops that a packet needs to make is smaller since less switching layers are being deployed in the network.

During a period of 42 months, the L3MATRIX project brought together leading European companies, universities, and research institutes with great expertise and experience in silicon photonics, III-V materials, and 3D device integration. The consortium was led by Fraunhofer Institute for Reliability and Microintegration IZM as project coordinator and Dust Photonics (Israel) as technology manager. Further partners were ams (Austria), IBM Research (Switzerland), Aristotelio Panepistimio Thessalonikis (Greece), University Politecnica de Valencia (Spain), Bright Photonics (Netherlands), and University College London (United Kingdom). The novel approach focused on embedding III-V sources on the SOI substrate which eliminates the need to use an external light source for the modulators and their co-integration with the switching ASIC. L3MATRIX provided a new method of building switching elements that are both high radix and have an extended bandwidth of 25 Gb/s in single mode fibers and waveguides with low latency. The power consumption of DC networks built with these devices is ten-fold lower compared to the conventional technology. The overall research and development budget of the project was about 3.8 million euros with 3.1 million euros EU contribution, which allowed an effort of more than 420 person-months for the duration of the project.

The outcome of the L3MATRIX project was to demonstrate the basic building blocks of a co-packaged optical system. Two dimensional silicon photonics arrays with 64 modulators were fabricated in the fab. Novel modulation schemes based on slow light modulation have been developed to assist in achieving efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Packaging of these 2D photonic arrays in a chiplet configuration has been demonstrated using a vertical integration approach in which the optical interconnect matrix was flipchip assembled on top of CMOS mimic chip with 2D vertical fiber coupling. The optical chiplet was further assembled on a substrate to facilitate integration with the multi-chip module of the co-packaged system with a switch surround by several such optical chiplets

A proactive Intellectual Property Rights management strategy was successfully deployed resulting in L3MATRIX foreground innovations being captured in six patents.

Regarding the dissemination of L3MATRIX foreground knowledge to the scientific community, during the lifetime of the project, more than 45 publications in journals were generated and more than 50 “other dissemination actions” that included invited talks to prestigious conferences in photonics, workshop presentations etc. Moreover, L3MATRIX organized three successful symposia on optical interconnects with more than 150 attendees at each event.

The main project results and technologies are now available to small and medium-sized enterprises for further development, for deep characterization of system embedded photonic interconnect, and for validation in data center environments within ‘PhoxLab – European Photonics Innovation Hub for Optical Interconnects’ at the Fraunhofer IZM in Berlin. (Source: Fh. IZM)

Link: L3MATRIX project, Fraunhofer Institute for Reliability and Microintegration IZM, Berlin, Germany

Speak Your Mind

*